{"id":7157,"date":"2026-08-17T14:22:40","date_gmt":"2026-08-17T14:22:40","guid":{"rendered":"https:\/\/couleenergy.com\/?p=7157"},"modified":"2026-08-17T14:22:43","modified_gmt":"2026-08-17T14:22:43","slug":"cell-to-module-ratio-explained-etfe-fiberglass-modules","status":"publish","type":"post","link":"https:\/\/couleenergy.com\/de\/cell-to-module-ratio-explained-etfe-fiberglass-modules\/","title":{"rendered":"Zell-zu-Modul-Verh\u00e4ltnis bei ETFE-Modulen: Warum 33 Solarzellen nicht die Nennleistung ergeben"},"content":{"rendered":"\n
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An OEM buyer emailed us last quarter with one very good question. His cell spec said 26.2% efficiency. His panel held 33 half-cut cells at roughly 4.37 W each, which multiplies out to 144.2 W. So why did the label say 130 W?<\/p>\n \n

Fourteen watts, apparently missing.<\/p>\n \n

Nothing was wrong with the solar panel. That gap has a name, a formula and a well-mapped set of causes \u2014 engineers call it the cell-to-module (CTM) ratio<\/strong>. What follows walks the arithmetic on a real 130 W ETFE back-contact solar module, hands you three checks you can run on any datasheet in a minute, and settles a question we field almost weekly: does the fiberglass layer eat your power?<\/strong><\/p>\n \n<\/div>\n\n\n\n\n\n

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\n What CTM actually measures\n <\/h2>\n \n

CTM compares two numbers: the sum of the individual cell powers, flash-tested before lamination, against the finished module’s rated power at STC.<\/p>\n \n

\n CTM (%) = Module power ÷ Sum of cell powers × 100<\/span>\n <\/div>\n \n

A ratio below 100% is ordinary. Building cells into a module adds film, adhesive, gaps, conductors and resistance, and each charges a small toll.<\/p>\n \n

What surprises buyers is that CTM can climb above<\/em> 100%. Fraunhofer ISE has built half-cell modules at 104% CTM<\/a> by deliberately engineering optical gains into the stack. At industry scale the crossover already happened: according to ITRPV data CTM passed the 100% benchmark in 2021<\/a>, with half-cell designs above 100.5% and three-cut designs near 101%.<\/p>\n \n

A module, in other words, is not a box that loses light. It is an optical system, and parts of it hand power back.<\/p>\n \n<\/div>\n\n\n\n

\"CTM
CTM 100+ \u2013 Improving Module Performance, Fraunhofer ISE<\/figcaption><\/figure>\n\n\n\n\n\n
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\n The trap: dividing module efficiency by cell efficiency\n <\/h2>\n \n

One mistake shows up in procurement spreadsheets more than any other. A buyer sees 20.2% module efficiency and 26.2% cell efficiency, divides, lands on 77.1%, and reports that the factory is losing 23% in lamination.<\/p>\n \n

The number is wrong, and the reason is structural rather than arithmetic. Cell efficiency is measured over the cell area; module efficiency is measured over the whole panel.<\/strong> A panel carries edges, cell gaps and routing space \u2014 none of it makes power, and none of it belongs in a lamination loss figure.<\/p>\n \n

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The correct relationship<\/p>\n

Module efficiency = Cell efficiency × Active-area coverage × CTM ratio<\/p>\n <\/div>\n \n

Split the two effects and the numbers stop looking suspicious. One is geometry, fixed by layout; the other is integration physics, fixed by process. Lumping them together hides the only one you can actually negotiate.<\/p>\n \n<\/div>\n \n\n\n\n\n\n

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\n A worked example: 130 W of flexible back contact\n <\/h2>\n \n

Take a real product \u2014 a 1090 × 590 mm ETFE back-contact flexible module, 33 half-cut cells in a 3 × 11 array, rated 130 W at STC.<\/p>\n \n \n \n \n \n \n \n \n \n \n \n \n \n
Schritt<\/th>\n Berechnung<\/th>\n Ergebnis<\/th>\n <\/tr>\n <\/thead>\n
Full cell area<\/td>\n 182 × 183.75 mm<\/td>\n 0.0334 m²<\/td>\n <\/tr>\n
Full cell power at 26.2%<\/td>\n 0.0334 × 1000 × 0.262<\/td>\n ~8.75 W<\/td>\n <\/tr>\n
Half-cut cell power<\/td>\n 8.75 ÷ 2<\/td>\n ~4.37 W<\/td>\n <\/tr>\n
Sum of 33 half-cells<\/td>\n 33 × 4.37<\/td>\n 144.2 W<\/strong><\/td>\n <\/tr>\n
Rated module power<\/td>\n Datasheet, STC<\/td>\n 130 W<\/strong><\/td>\n <\/tr>\n
CTM ratio<\/strong><\/td>\n 130 ÷ 144.2<\/td>\n 90.2%<\/strong> — a 14.2 W gap<\/td>\n <\/tr>\n <\/tbody>\n <\/table>\n \n

Next, the geometry. Each half-cell measures roughly 91 × 183.75 mm, so 33 of them cover about 0.552 m². The panel spans 0.643 m². Active coverage therefore sits near 85.8%<\/strong>.<\/p>\n \n

Multiply the three together:<\/p>\n \n

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26.2% × 85.8% × 90.2% = 20.3%<\/strong><\/p>\n

The datasheet claims 20.2%. That is rounding, not a discrepancy.<\/p>\n <\/div>\n \n

We recommend this reconciliation to every buyer, because it is fast and hard to fake. If a supplier’s three numbers refuse to close within a few tenths, something is off \u2014 an inflated cell efficiency, a misstated area, or a datasheet borrowed from someone else’s product.<\/p>\n \n

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Two refinements the arithmetic hides<\/p>\n

Chamfers.<\/strong> A 182 × 183.75 mm rectangle has a 258.6 mm diagonal and will not fit a 252 mm ingot, so the host wafer is pseudo-square. True cell area runs slightly under the rectangle and measured CTM lands a few tenths higher. The identity self-corrects: shrink cell area and coverage falls while CTM rises, leaving module efficiency untouched.<\/p>\n

Tolerance.<\/strong> A 0 to +3% tolerance sets the nameplate at the bottom of the production distribution, so any CTM derived from the label understates what the line achieves.<\/p>\n <\/div>\n \n

Two more checks, and neither needs a lab<\/h3>\n \n

The efficiency reconciliation is the thorough test. These two take a minute and catch fabricated datasheets outright.<\/p>\n \n

Volts per cell.<\/strong> Divide the module voltages by the cell count: 20.13 V ÷ 33 = 0.61 V at maximum power, 23.45 V ÷ 33 = 0.71 V open-circuit. Both land where back-contact silicon belongs. Come out at 0.5 or 0.9 V and either the cell count is wrong or the electrical data was invented.<\/p>\n \n

Current density.<\/strong> Divide short-circuit current by one cell’s active area \u2014 in a series string every cell carries the same current. Here: 6.77 A ÷ 167.2 cm² = 40.5 mA\/cm²<\/strong>.<\/p>\n \n

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The physics ceiling<\/p>\n

Richter, Hermle and Glunz put the intrinsic limit for single-junction crystalline silicon at 43.31 mA\/cm²<\/a> \u2014 an ideal 110 µm cell with perfect light trapping and no front metallisation. Nothing built from silicon beats it. At 40.5 mA\/cm², this module reaches about 94% of that ceiling: tight, but legal, and consistent with a back-contact cell carrying no front gridlines.<\/p>\n <\/div>\n \n

Treat it as a red line. A datasheet implying more than roughly 43 mA\/cm² is not optimistic; it is impossible. We have seen quoted figures clear 46. One caution: where cells sit in parallel groups rather than a single series string, divide module current by the number of parallel strings first.<\/p>\n \n<\/div>\n \n\n\n\n\n\n

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\n Where the missing 14 watts actually go\n <\/h2>\n \n

That 9.8% is not one thing. It is at least six, and only some of them involve light at all.<\/p>\n \n \n \n \n \n \n \n \n \n \n \n
Mechanism<\/th>\n Ursache<\/th>\n Fixable at the factory?<\/th>\n <\/tr>\n <\/thead>\n
Cell cutting<\/strong><\/td>\n Recombination and micro-damage at the cut edge<\/td>\n Yes \u2014 separation method, edge passivation<\/td>\n <\/tr>\n
Front-side optics<\/strong><\/td>\n Reflection and absorption through the front stack<\/td>\n Yes \u2014 material grade, lamination quality<\/td>\n <\/tr>\n
Interconnection<\/strong><\/td>\n I²R heating in rear conductors and joints<\/td>\n Yes \u2014 conductor cross-section, joint integrity<\/td>\n <\/tr>\n
Mismatch<\/strong><\/td>\n 33 cells in series; the weakest sets the current<\/td>\n Yes \u2014 tighter binning<\/td>\n <\/tr>\n
Junction box & cable<\/strong><\/td>\n Diode and lead resistance<\/td>\n Partly \u2014 small, but real<\/td>\n <\/tr>\n
Optical gains<\/strong><\/td>\n Index coupling and light recycled off the rear layers<\/td>\n Yes \u2014 and this one adds<\/em> power<\/td>\n <\/tr>\n <\/tbody>\n <\/table>\n \n

That last row is why you cannot estimate CTM by multiplying transmittance figures off four supplier datasheets. Fraunhofer’s modelling puts gains and losses in the same ledger, not in a chain of subtractions.<\/p>\n \n

Splitting optical loss from electrical loss<\/h3>\n \n

Six mechanisms in one number is not much use when you are trying to fix something. The split is easy, though, and it turns on which parameter each mechanism damages. Optical losses cost photons, so they show up in current. Electrical losses cost voltage and fill factor, and leave current largely alone.<\/p>\n \n

So ask for flash data both sides of lamination and compute two ratios:<\/p>\n \n